Static random access memory (SRAM) cells are popular for their high performance and low cost. In cache applications, particularly at L1 and L2 levels, six-transistor (6T) or eight-transistor (8T) SRAM cells are widely employed due to their high speed and process compatible cell structure. In applications requiring high storage amounts, however, for example, in L3 cache or memories with 32M bits or higher, one-transistor (1T) RAM cells with dynamic random access memory (DRAM) cells are preferred for their low chip area requirement. To achieve both high performance and high storage, SRAM and 1T DRAM memories are often integrated on one chip.
The conventional memory chip formation, however, suffers drawbacks. Typically, the local interconnection in an SRAM cell, for example, a drain region of a pull-up MOS device and a drain region of a pull-down device are typically connected using the first metallization layer (M1). Bitlines, wordlines and power lines thus have to use metallization layers two and three. Therefore, at least three metallization layers are needed just for the formation of SRAM cells. Another drawback is that contact plugs connecting the source/drain regions of MOS devices in SRAM cells are tall contact plugs extending from M1 all the way down to source/drain regions of MOS devices. The long contact plugs combined with the high device density of memory cells results in high parasitic capacitances. RC delay is thus increased.
What is needed in the art, therefore, is a memory structure that combines 1T DRAM and 6T (or more) SRAM therein to take advantage of the benefits associated with high performance and high density while at the same time overcoming the deficiencies of the prior art.